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ISL95810
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet October 7, 2005 FN8090.1
Low Noise, Low Power I2C Bus, 256 Taps
The ISL95810 integrates a digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. The content of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP's IVR to the WR. The DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 256 resistor taps - 0.4% resolution * I2C serial interface * Wiper resistance: 70 typical @ 3.3V * Non-volatile storage of wiper position * Standby current 5A max * Power supply: 2.7V to 5.5V * 50k, 10k total resistance * High reliability - Endurance: 200,000 data changes per bit per register - Register data retention: 50 years @ T 75C * 8 Ld MSOP and 8 Ld TDFN packaging * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER ISL95810WIU8* ISL95810WIU8Z* (Note) ISL95810WIRT8Z* (Note) ISL95810UIU8* ISL95810UIU8Z* (Note) ISL95810UIRT8Z* (Note) *Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. AIT AOK 50 TEMP PART RTOTAL (k) RANGE (C) MARKING AIU 10 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld 3 x 3 TDFN (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld 3 x 3 TDFN (Pb-free)
Pinout
ISL95810 (8 LD MSOP) TOP VIEW
WP SCL SDA GND 1 2 3 4 8 7 6 5 VCC RH RL RW
ISL95810 (8 LD TDFN) TOP VIEW
WP 1 SCL 2 SDA 3 GND 4
8 VCC 7 RH 6 RL 5 RW
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL95810 Block Diagram
VCC
RH
SDA SCL WP I2C AND CONTROL
WIPER REGISTER RW NON-VOLATILE REGISTER RL
GND
Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 SYMBOL WP SCL SDA GND RW RL RH VCC DESCRIPTION Hardware write protection. Active low. Prevents any "Write" operation of the I2C interface. I2C interface clock Serial data I/O for the I2C interface Ground "Wiper" terminal of the DCP "Low" terminal of the DCP "High" terminal of the DCP Power supply
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Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at Any Digital Interface Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at Any DCP Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL RTOTAL RW CH/CL/CW ILkgDCP INL (Note 6) DNL (Note 5)
Over recommended operating conditions unless otherwise stated. PARAMETER TEST CONDITIONS W, U versions respectively -20 VCC = 3.3V @ 25C Wiper current = VCC/RTOTAL 70 10/10/25 Voltage at pin from GND to VCC -1 Monotonic over all tap positions W option U option W option U option DCP Register set to 80 hex W option -0.75 U option -0.5 0 0 -7 -2 1 0.5 -1 -0.5 4 0.1 1 1 -0.75 -0.5 7 2 0 0 ppm/C LSB (Note 2) MIN TYP (Note 1) 10, 50 +20 200 MAX UNIT k % pF A LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2)
RH to RL Resistance RH to RL Resistance Tolerance Wiper Resistance Potentiometer Capacitance (Note 13) Leakage on DCP Pins (Note 13) Integral Non-Linearity Differential Non-Linearity
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
ZSerror (Note 3) Zero-Scale Error FSerror (Note 4) Full-Scale Error TCV (Note 7, 13) Ratiometric Temperature Coefficient RINL (Note 11) RDNL (Note 5) Integral Non-Linearity Differential Non-Linearity
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) DCP register set between 20 hex and FF hex. Monotonic over all tap positions -1 1 -0.75 -0.5 1 0.5 45 7 2 MI (Note 8) MI (Note 8) MI (Note 8) MI (Note 8) MI (Note 8) ppm/C
DCP register set between 20 hex W option -0.75 and FF hex. Monotonic over all tap U option -0.5 positions W option U option 0 0
Roffset (Note 9) TCR (Note 12, 13)
Offset
Resistance Temperature Coefficient DCP register set between 20 hex and FF hex
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 (Note 15) ICC2 (Note 15) ISB (Note 15) PARAMETER VCC Supply Current (Volatile write/read) VCC Supply Current (Nonvolatile Write) VCC Current (Standby) TEST CONDITIONS Read and Volatile Write States only) fSCL = 400kHz; SDA = Open; (for I2C, Active, MIN TYP (Note 1) MAX 1 3 5 2 UNITS mA mA A A
fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) VCC = +5.5V, I2C Interface in Standby State VCC = +3.6V, I2C Interface in Standby State
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL ILkgDig tDCP (Note 13) Vpor VCCRamp tD (Note 13) PARAMETER Leakage Current, at Pins SDA, SCL, and WP Pins DCP Wiper Response Time Power-On Recall Voltage VCC Ramp Rate Power-Up Delay VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 200,000 Temperature 75C 50 -0.3 0.7*VCC 0.05* VCC 0 0.4 10 400 50 900 1300 0.3*VCC VCC+0.3 TEST CONDITIONS Voltage at pin from GND to VCC SCL falling edge of last bit of DCP Data Byte to wiper change Minimum VCC at which memory recall occurs 1.8 0.2 3 MIN -10 TYP (Note 1) MAX 10 1 2.6 UNITS A s V V/ms ms
EEPROM SPECIFICATIONS EEPROM Endurance EEPROM Retention SERIAL INTERFACE SPECIFICATIONS VIL VIH WP, SDA, and SCL Input Buffer LOW Voltage WP, SDA, and SCL Input Buffer HIGH Voltage V V V V pF kHz ns ns ns Cycles Years
Hysteresis (Note 13) SDA and SCL Input Buffer Hysteresis VOL (Note 13) Cpin (Note 13) fSCL tIN (Note 13) tAA (Note 13) tBUF (Note 13) SDA Output Buffer LOW Voltage, Sinking 4mA WP, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at Any pulse narrower than the max spec is SDA and SCL Inputs suppressed. SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window.
Time the Bus Must be Free Before SDA crossing 70% of VCC during a STOP the Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition. Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Input Data Hold Time STOP Condition Setup Time STOP Condition Hold Time for Read, or Volatile Only Write STOP Condition Hold Time for Non-Volatile Write Output Data Hold Time SDA and SCL Rise Time Measured at the 30% of VCC crossing. Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. From 30% to 70% of VCC
tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tHD:STO tHD:STO:NV tDH (Note 13) tR (Note 13)
1300 600 600 600 100 0 600 600 2 0 20 + 0.1 * Cb 250
ns ns ns ns ns ns ns ns s ns ns
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tF (Note 13) Cb (Note 13) Rpu (Note 13) PARAMETER SDA and SCL Fall Time TEST CONDITIONS From 70% to 30% of VCC MIN 20 + 0.1 * Cb 10 1 TYP (Note 1) MAX 250 400 UNITS ns pF k
Capacitive Loading of SDA or SCL Total on-chip and off-chip SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k Before START condition After STOP condition
tWP (Notes 13, 14) Non-Volatile Write Cycle Time tSU:WP tHD:WP WP Setup Time WP Hold Time 600 600
12
20
ms ns ns
SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tHD:STA
tAA SDA (OUTPUT TIMING)
tDH
tBUF
WP Pin Timing
START SCL CLK 1 STOP tHD:STO tHD:STO:NV
SDA IN tSU:WP WP tHD:WP
NOTES: 1. Typical values are for TA = 25C and 3.3V supply voltage. 2. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = V(RW)0/LSB. 4. FS error = [V(RW)255 - VCC]/LSB. 5. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 6. INL = [V(RW)i - (i * LSB - V(RW)0)]/LSB for i = 1 to 255. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 7. TC V = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 240 decimal, T = -40C to 85C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R255 - R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. Roffset = R0/MI, when measuring between RW and RL. 9. Roffset = R255/MI, when measuring between RW and RH. 10. RDNL = (Ri - Ri-1)/MI, for i = 32 to 255. 11. RINL = [Ri - (MI * i) - R0]/MI, for i = 32 to 255. [ Max ( Ri ) - Min ( Ri ) ] 10 12. TC R = --------------------------------------------------------------- x ---------------- for i = 32 to 255, T = -40C to 85C. Max( ) is the maximum value of the resistance and Min ( ) is the [ Max ( Ri ) + Min ( Ri ) ] 2 125C minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested.
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14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. VIL = 0V, VIH = VCC
Typical Performance Curves
160 VCC = 2.7, T = 85C 140 WIPER RESISTANCE () 120 100 80 60 40 20 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) VCC = 5.5, T = -40C VCC = 5.5, T = 85C VCC = 5.5, T = 25C STANDBY ICC (A) VCC = 2.7, T = -40C VCC = 2.7, T = 25C 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.7 3.2 25C 3.7 4.2 VCC (V) 4.7 5.2 85C -40C
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC / RTOTAL ] for 50k (U)
FIGURE 2. STANDBY ICC vs VCC
0.2 0.15 0.1 DNL (LSB)
0.3 VCC = 5.5, T = -40C VCC = 2.7, T = 25C VCC = 2.7, T = -40C 0.2 0.1 INL (LSB) 0 -0.1 VCC = 5.5, T = 25C VCC = 2.7, T = 85C VCC = 5.5, T = 85C -0.2 -0.3 50 100 150 200 250 TAP POSITION (DECIMAL)
VCC = 2.7, T = -40C VCC = 5.5, T = -40C
VCC = 5.5, T = 85C
0.05 0 -0.05 -0.1 -0.15 -0.2 0
VCC = 2.7, T = 25C VCC = 2.7, T = 85C VCC = 5.5, T = 25C
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
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ISL95810 Typical Performance Curves
(Continued)
0.4
0 -0.1
0.35 FSerror (LSB)
-0.2 -0.3
VCC = 5.5V
ZSerror (LSB)
0.3 2.7V 0.25
-0.4 -0.5 -0.6 -0.7 VCC = 2.7V
0.2
5.5V
-0.8 -0.9
0.15 -40
-20
0
20
40
60
80
-1 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
0.3 VCC = 2.7, T = 25C 0.2 0.1 DNL (LSB) INL (LSB) 0 -0.1 VCC = 5.5, T = 85C -0.2 -0.3 32 VCC = 2.7, T = 85C VCC = 2.7, T = -40C VCC = 5.5, T = -40C 232 VCC = 5.5, T = 25C
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 VCC = 2.7, T = 85C VCC = 5.5, T = 25C -0.5 32 82 132 VCC = 2.7, T = -40C 182 232 VCC = 5.5, T = -40C VCC = 5.5, T = 85C VCC = 2.7, T = 25C
82
132 182 TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
1.50 END TO END RTOTAL CHANGE (%) 1.00
20
10 0.50 0.00 5.5V TC (ppm/C) 2.7V
0
-0.50 -1.00 -1.50 -40
-10
-20
0
20
40
60
80
-20 32
82
132
182
232
TEMPERATURE (C)
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
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ISL95810 Typical Performance Curves
(Continued)
35 INPUT 25 15 TC (ppm/C) 5 -5 -15 -25 32 Tap Position = Mid Point RTOTAL = 9.4K 57 82 107 132 157 182 207 232 OUTPUT
TAP POSITION (DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
Signal at Wiper (Wiper Unloaded)
SCL
Signal at Wiper (Wiper Unloaded Movement From ffh to 00h)
Wiper Movement Mid Point From 80h to 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
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ISL95810 Principles of Operation
The ISL95810 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory, and a I2C serial interface providing direct communication between a host and the potentiometer and memory. * A write operation to addresses 0 writes the same value to the WR and IVR of the corresponding DCP. When the byte at address 2 is 80h (128 decimal): * A read operation to addresses 0 outputs the value of the volatile WR. * A write operation to addresses 0 only writes to the corresponding volatile WR. It is not possible to write to an IVR without writing the same value to its corresponding WR. 00h and 80h are the only values that should be written to address 2. All other values are reserved and must not be written to address 2. The ISL95810 is pre-programed with 80h in the IVR.
TABLE 1. MEMORY MAP ADDRESS 2 1 0 IVR NON-VOLATILE Reserved WR VOLATILE Access Control
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). The DCP has its own WR. When the WR of the DCP contains all zeroes (WR<7:0>: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR of the DCP contains all ones (WR<7:0>: FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL95810 is being powered up, The WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading, the ISL95810 reads the value stored in non-volatile Initial Value Registers (IVRs) and loads it into the WR. The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections.
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The ISL95810 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL95810 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Memory Description
The ISL95810 volatile and non-volatile registers are accessed by I2C interface operations at addresses 0 and 2 decimal. The non-volatile byte at addresses 0 contains the initial value loaded at power-up into the volatile Wiper Register (WR) of the DCP. The byte at address 1 is reserved; the user should not write to it, and its value should be ignored if read. The volatile WR, and the non-volatile Initial Value Register (IVR) of the DCP are accessed with the same Address Byte, set to 00 hex in both cases. A volatile byte at address 2 decimal, controls what byte is read or written when accessing DCP registers: the WR, the IVR, or both. When the byte at address 2 is all zeroes, which is the default at power-up: * A read operation to addresses 0 outputs the value of the non-volatile IVR.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power-up of the ISL95810 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95810 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 15). A START condition is ignored during the powerup sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation to
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ISL95810
volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 16). The ISL95810 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL95810 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 as the seven MSBs. The LSB in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 2).
TABLE 2. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 0 0 0 R/W (LSB)
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL95810
01 01 0 000 A C K
000000 A C K A C K
FIGURE 17. BYTE WRITE SEQUENCE
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S T A R T S T A IDENTIFICATION R BYTE WITH T R/W=1
SIGNALS FROM THE MASTER
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
A C K
A C K
S T O P
SIGNAL AT SDA
01010000 A C K
000000 A C K
01010001 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 18. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95810 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95810 begins its internal write cycle to non-volatile memory. During the internal nonvolatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95810 enters its standby state (See Figure 17). The byte at address 02h determines if the Data Byte is to be written to volatile and/or non-volatile memory (See "Memory Description" on page 7).
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL95810 responds with an ACK. Then the ISL95810 then transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (See Figure 18). The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory (See "Memory Description" on page 9.)
Data Protection
The WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW) the device ignores Data Bytes of a Write Operation, does not respond to the Data Bytes with an ACK, and instead, goes to its standby state waiting for a new START condition. A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory.
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ISL95810 MSOP Packaging Information
8-Lead Plastic, MSOP, Package Code U8
0.118 0.002 (3.00 0.05) 0.012 + 0.006/-0.002 (0.30 + 0.15/-0.05) 0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 Typ.
0.040 0.002 (1.02 0.05)
0.008 (0.20) 0.004 (0.10)
0.0256" Typical
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) Ref. 0.193 (4.90) Ref.
0.025" Typical 0.220"
NOTE: 1.ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
FOOTPRINT
0.020" Typical 8 Places
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FN8090.1 October 7, 2005
ISL95810 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X A 0.15 C A D 2X 0.15 C B
L8.3x3B
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A3 b D 0.23 2.15 1.35 0.20 0.20 MIN 0.70 NOMINAL 0.75 0.20 REF 0.30 3.00 BSC 2.30 3.00 BSC 1.50 0.65 BSC 0.30 8 4 0.40 1.60 2.40 0.38 MAX 0.80 0.05 NOTES 5, 8 7, 8 7, 8 8 2 3 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals.
E 6 INDEX AREA TOP VIEW B
D2 E
// 0.10 C 0.08 C
E2 e k L N Nd
A C SEATING PLANE SIDE VIEW
A3
D2 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2/2
7
8
NX k E2 E2/2
3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
NX L N 8 N-1 e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" (A1) L NX b 5 0.10 M C A B
CC e
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN8090.1 October 7, 2005

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